The present invention relates generally to the computer art. More particularly, the present invention relates to microcomputer main memory systems. Specifically, the present invention provides an improved memory system incorporating dual-port random access memory devices.
Microcomputer main memory systems typically incorporate dynamic random access memory (DRAM) devices. These devices store both instruction words and data words for use by the central processing unit (CPU). When an instruction word or data word is needed by the CPU, a memory access cycle is initiated. To complete this cycle, a finite time interval is needed, typically on the order of 200 nanoseconds, and this interval is dictated by the characteristics of the DRAM. During this interval the CPU is forced to wait for the DRAM to respond.
In order to overcome delays associated with memory access, sophisticated computer systems have employed a memory cache. A cache is a small block of extremely high speed memory used as a temporary holding buffer for information which is likely to be accessed by the CPU. Cache memory is much more expensive than DRAM devices and is thus used in limited quantity. When the CPU fetches information from main memory, the cache is first checked to determine if the information which is being fetched is already present in the cache. If so, the information is routed directly from the cache to the processor with very little delay. Otherwise, it is necessary to perform a slower access to main memory for the desired information. Such access also results in updating the cache with the information stored in main memory locations located nearby the most recently accessed main memory word. In theory, it is this information that is most likely to be subsequently accessed and, thus, will be present in the cache for quick access.
The cache system works well where the CPU is repeatedly accessing words within a small block, such as a small program segment. As programs grow larger, however, the probability of a desired word at any time being in the cache decreases for a given cache size. Consequently, performance suffers since a larger portion of memory accesses will be spent loading instructions from main memory to the cache, rather than usefully manipulating data. A larger cache can remedy this, but at a great increase in system cost.
Accordingly, a principal object of the present invention is to provide a high speed main memory system that generally overcomes the deficiencies of the prior art.
A more detailed object of the present invention is to provide a simplified cache that is low cost and thus adaptable for microcomputer use.
Yet another object lies in providing a cache that exploits the generally sequential nature of instruction access events.
The present invention generally utilizes a video RAM memory device in association with a main memory unit for a micro-computer system. Through the use of the V-RAM, random access may be provided to dynamic RAM cells or the content of the cells may be sequentially read from the memory. In conjunction with the V-RAM, a multiplexer provides for selection of the appropriate output from the memory. Additionally, a controller controls the transfer of data from the V-RAM and also controls the operation of the multiplexer device. Additional features are embodied in the use of a latch for storing the address of an immediately, previously executed word. In association with the latch, an incrementor responsive to the contents of the latch may develop an address corresponding to an instruction word physically located upwardly and adjacent to the immediately, previously executed word. In association with the latch and the incrementor, a comparator may evaluate the coincidence between the developed address value and a current instruction word address. The output of the comparator then controls whether the contents of a shift register are modified or not. If there is an address match, the next instruction is read from a sequential output port; if not, the next instruction is retrievely conventionally. A corresponding method for implementation of the invention of the present application generally comprises comparing the address of an instruction word with the incremented address of an immediately, previously executed word and then shifting the contents of an associated shift register for output. The appropriate instruction at a serial port.
The appended claims set forth the features of the present invention with particularity. The invention, together with its objects and advantages, may be best understood from the following detailed description taken in conjunction with the accompanying drawings of which: